FPGA Implementation Mix Column for BCF Algorithm

Dini Siti Nurmahmudah; Erik Haritman; Muhammad Adli Rizqulloh; Resa Pramudita; Roer Eka Pawinanto; Agus Ramelan; Nike Sartika

doi:10.1109/ICWT58823.2023.10335469

FPGA Implementation Mix Column for BCF Algorithm

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Dini Siti Nurmahmudah, Erik Haritman, Muhammad Adli Rizqulloh, Resa Pramudita, Roer Eka Pawinanto, Agus Ramelan, Nike Sartika

2023 Proceeding of 2023 9th International Conference on Wireless and Telematics, ICWT 2023 Conference paper Cited by 0

Abstract

Block Cipher Four Algorithm is used to protect data. BCF Architecture has been developed, but MixColoumn operation in that architecture become bottleneck. In this paper, we proposed fast MixColoumn architecture using parallel computing technique. Fast MixColoumn architecture can reduce 128 bit Encryption opereation clock from 182 to 122 clock. As a trade off, the number of Logic Elements and Registers required by the Fast MixColumn Architecture is 1.16 and 1.68 more. The Fast MixColoumn architecture offers a maximum speed of 1.15 times faster. © 2023 IEEE.

Affiliations

Indonesian University of Education, Electrical Engineering, Bandung, Indonesia; Indonesian University of Education, Automation and Robotics Engineering Education, Bandung, Indonesia; Sebelas Maret University, Electrical Engineering, Surakarta, Indonesia; Sunan Gunung Djati State Islamic University Bandung, Electrical Engineering, Bandung, Indonesia

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